A hardware architecture implementation of Advanced Encryption Standard (AES) is globally adopted to encrypt data for variant communications systems, taking into account that AES is reliable, secured and immunized against attacks. A single crypto system is suggested to encrypt and/or decrypt different types of data .These types of data are assumed to be as a text data .The image is considered as a case study for the type of data that is to be encrypted in real time. Then the proposed architectures are used to encrypt the video within the time ≤ 33 m sec . Two architectures are proposed . The first one is a hybrid of both stream and block ciphering. This architecture is used to increase the encryption security by reducing the correlation among image pixels. The resulting encryption time for an image of (32x64)pixels is equal to 16.76 µ sec. The second architecture is proposed for CTR mode of AES algorithm. The same time achieved in the first architecture is also achieved in this implementation. However ,the half of the hardware resources in comparison with the first architecture is achieved in implementing the second, but if it is used for either encryption or decryption , not for both simultaneity. The real time implementation is achieved due to using parallel computation that is based on pipelining technique. The architecture are synthesized on Spartan-6 LX(XC6SLX16) using ISE 14.2 .