Authors

Abstract

Abstract
In this paper, lattice structures for DWT are introduced through the design and FPGA implementations of the orthogonal Daubechies filter banks of orders 2, 4, 6 and 8. Multipliers and shift-add methods are both used to perform multiplication operations for these types of filter banks. Two implementation techniques are introduced, namely; the pipelining technique that is efficient from the throughput point of view, and the area efficient bit-serial implementation technique. The obtained results show the ability to achieve high throughput using pipelining (with 2 output samples / clock) on behalf of the area allocation. While bit-serial technique minimizes the allocated area on behalf of the throughput which may decrease with increasing filter order. As compared with other recent implementations, the results of implementing the designed filter banks using the SPARTAN-3E FPGA kit are efficient in minimizing implementation complexity to 0.584 - 0.712 of its corresponding values for different structures in recent hardware implementations. It is also obtained that the resulting structures can operate at high frequencies (up to 47.09 MHz).

Keywords