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Abstract

Abstract

This paper develops a system level architecture for implementing a cost-efficient, FPGA-based reconfigurable two dimensional (2D) FFT system. The adopted approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput). These two extremes are optimized based on using run time reconfiguration, double buffering technique, shared Dual Ported RAM (DPRAM) modules and the “hardware virtualization” to reuse the available processing components. The system employs two one Dimensional (1D) FFT processor each with sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT engine. Thus the architecture supports transform length of 256X256 complex points, as a demonstrator to the design idea, using fixed-point arithmetic and has been developed using radix-4 butterfly architecture. The simulation results that have been performed using VHDL modeling language and ModelSim software shows that the full design can be implemented using single FPGA platform requiring about 50,000 Slices.
Keywords: 2D Fast Fourier Transform Radix-4. Run Time Reconfiguration

Keywords