In this paper, a hardware computing unit has been designed and implemented. This unit computes many elementary functions (such as sine, cosine, tan-1, sinh, cosh, and square root) that their computing by using software systems requires thousands of clock cycles as an execution time. The architecture of the function computation has been designed by using VHDL and placed on XC3S500E FPGA chip in Spartan 3E as a target technique. In this paper, two algorithms have been used in computing the mathematical functions, because they can be implemented using FPGA chip. The first is the Coordinate Rotation Digital Computer algorithm (CORDIC) which was introduced in 1959. It is a single unified algorithm for calculating many elementary functions including trigonometric, hyperbolic, logarithmic and exponential functions, multiplication, division and square root. The second one uses the lookup table. According to the self-similarity in the trigonometric functions, and using the techniques of parallel pipelining for the CORDIC algorithm, speedup of (24.7 - 30.3)×100% is obtained as compared with the other parallel architectures. The throughput became operation/clock pulse except the first operation whose latency was 32 clock pulse.
Keywords: CORDIC, lookup table, Elementary Function, FPGA