This paper presents a new, expandable, pipelined linear array architecture designed for transparently tolerating processor failures for real-time DSP applications. The proposed system use twelve TMS320C40 DSP processors ( Processor Modules PMs ) to construct ten stages pipelined system with two spare processors (SPs). However, the system can be expanded to increase the pipeline stages and the performance, and adding more spare processors to increase the dependability and reliability of the system. In Proposed scheme, the system can automatically reconfigure itself in the event of failure in one or two of its DSP processors and the computations continue unhindered without noticeable performance degradation. Each DSP processor communicates with neighboring processors through a high speed communication ports ( commport ). Some of these commports in every processor are used as a bypass links in case of failure of one or two processors. The system uses the forward-task-shift (FTS) mechanism to tolerate the fault by assigning the function of the failed processor to the next fault-free processor.
Keywords- Linear processor array, fault tolerant, bypass links, pipelining, TMS320C40, DSP processors.