FPGA Implementations of Single-Multiplier Digital Sine-Cosine Wave Generators

This paper presents four different realizations of single-multiplier sine-cosine generators based on second-order digital filter structure. FPGA implementations of these four realizations are carried out on FPGA Spartan-3E Kit. Implementation results are compared from the view points of utilization resources and maximum frequency of operation. Another comparison is made between one of implementations of the derived structures and other two recent CORDIC-based implementations. The comparison results indicate that smaller chip area can be achieved in the case of the proposed structure of the sine-cosine generator. In addition, such structure can operate with higher circuit frequency as compared with the two others.


Introduction
Analog circuits can be used to build sine-cosine wave generators, but the control of the signal parameters is usually difficult.Another easily-controlled, flexible and costeffective method is to digitally implement such generators.Digital sine-cosine generators have many important practical applications as oscillators in several fields such as orthogonal communication systems, control systems, signal processing systems (e. g., the computation of the Discrete Fourier Transform (DFT)) and instrumentations.
Critically-stable second order structures can generate digital sine-cosine waves according to the angle value that entered to the realization and on the initial values of its variables.The conventional implementation methods of digital sine wave oscillators were first reported by J. Teirney, et al. [1] and improved by Schannerberger and Award [2].Implementation of recursive digital sine wave oscillator using the TMS32010 digital signal processer was introduced by I. Abu-El-Haija, et al. [3].J. Whittington, et al. [4] presented a digital sine-cosine generator implemented by FPGA chip as a frequency generator for TIGER radar application.
Recently, FPGA design and implementation of flexible and scalable digital sinecosine wave generator is reported by E. Garcia, et al. [5], based on pipelined CORDIC algorithm.Implementation of CORDIC algorithm for digital sine-cosine using FPGA Spartan-3E Kit is achieved by V. Kumer [6].Design, test and FPGA implementation for a reconfigurable calculation unit using some methods like a CORDIC algorithm, Look-Up-Table (LUT) and coordinate transformation to compute sine and cosine are also introduced in [7].In this paper, Implementations of four realizations of single-multiplier digital sine-cosine generators based on second order structures are considered using FPGA Spartan-3E Kit and compared to achieve the best proposed realization that takes less FPGA locations and can operate with a higher intermediate circuit frequency.In addition, the implementation of such best proposed realization is then compared with other two recent CORDIC-based implementations.The resulting reduced implementation facilitates the use of available technology to generate digital sine-cosine waves.This paper is organized as follows: Besides this introductory section, Section 2 contains different designs and realizations for single-multiplier digital sine-cosine generator.Section 3 describes the FPGA implementations of such generators.Results and comparisons are given in Section 4 to show the superiority of such single-multiplier digital sine-cosine generator realizations in FPGA implementations with the use of 32 bits word-length over two recent works.Finally, Section 5 concludes this paper.

Design and Realization of Single-Multiplier Digital Sine-Cosine Generators
The design and realization of digital sine-cosine oscillators are considered in this section.In particular, the design of digital sine-cosine generators that produce the two sinusoidal sequences that are exactly 90 degrees out of phase with each other is first discussed as follows: Let [ ] and [ ] denote the two outputs of a digital sine-cosine generator and given by [8]: Making use of ( 1) and ( 2), ( 3) and ( 4) can be written in matrix form as So, to obtain [ ] and [ ] from [ ] and [ ], respectively, two delay units are used in the corresponding structure.That's why digital sine-cosine signals can be generated using a second-order recursive digital filter with poles on the unit circle in the complex z-plane [9].Thus it is required to compare Eqn. ( 5) with the equivalent expression of a general second-order structure with no delay free loops in order to arrive at a realization of the single-multiplier sine-cosine generator.The general second-order structure is characterized by the following equation [8]: Expression (6) can be implemented using five multipliers as shown in Fig. 1.
By making some abbreviations in (6), it can be rewritten as Comparing Eqns.( 6) and ( 7), the values of A, C, D, E and F coefficients can be found.Expressing the multipliers and as functions of multiplier C, then Eqn. ( 6) can be written as It can be seen that, equation ( 8 In all these figures, Q represents the quantization process after multiplication.
Another method to generate digital sinecosine waves is by using a second-order critically-stable recursive digital filter with poles on the unit circle in the complex zplane.The difference equation of the digital system representing the direct form digital sine wave oscillator contains one multiplication operation and one subtraction and can be derived as follows [9], [11]: Let the generator output be Then and Fig. 4 A single-multiplier sine-cosine generator by setting ( ).
From the homogenous equations, the difference equation of second order can be written as follows To obtain a digital sine-cosine generator with different frequencies, the value of must be selected to be equal to The corresponding block diagram representation of ( 11) is shown in Fig. 5.

FPGA implementations of Single-Multiplier Digital Sine-Cosine Generators
The implementation of any architecture design in programming to a hardware device (such as FPGA) needs the knowledge of the components of the architecture design to make the mapping process of these components to the corresponding hardware components by using a hardware description language such as VHDL.Also an input-output management and different resource allocations must be taken in regard for any hardware implementation.The hardware implementation of the single-multiplier digital sine-cosine generator in Figs.There is more than one approach to describe any architecture design in programming.Each approach for the same architecture will have its own implementation that leads to different resource allocations in the synthesis level.The VHDL language requires very careful steps in order to have a satisfactory efficient implementation of the design to achieve an optimal FPGA design.These steps are as follows:

1) Handling delay elements
Single-multiplier digital sine-cosine generators are of second order structures.This means that there are two delay elements in their hardware implementations.These delay elements are used to synchronize the operations in the DSP structures and the timing should be handled carefully so that each signal could carry the right value at exactly the right time.In FPGA, the delay can be accomplished by simply performing an equating operation for the specified signal inside the edge condition of the system clock.This action forces the synthesizer to exploit a D-flip flop that causes the value of the signal to be stored for one clock.

2) Adders and multipliers
A single-multiplier digital sine-cosine generator contains usually three adders and one multiplier.The implementation of multiplier is done using an embedded multiplier 18 18 bits in FPGA [12].Since the dedicated multiplication process of the generators is of the size 32 32 bits, then four multipliers will be required to implement the multiplication process inside this FPGA.

3) Input-output management
It should be noted that the input to all realizations in Figs. 2 to 5 is cos(θ).The values of cos(θ) are stored in an array inside the FPGA as the inputs cos( )-cos( ) to the 16 Mux.By using the existed four switches (Sw0-Sw3) in SPARTAN-3E kit, the selection of desired angle can be treated as an input angle to the designed system.The output samples of sine and cosine signals are displayed using Liquid Crystal Display (LCD) screen in SPARTAN-3E kit.The LCD screen contains two lines; the first line displays the sine samples (SSam) while the second displays the cosine samples (CSam).
The hardware implementation of input-output unit is shown in Fig. 10.Number of bits to represent the inputs cos(θ) is 32 bits, number of bits to represent the integer part is 2 bits, while the rest 30 bits are used for fractional part, because the range of values for cos(θ) is between -1 and 1.

4) LCD screen to display results
Spartan-3E FPGA Starter Kit board prominently features a 2line by 16-character LCD.The FPGA controls the LCD via the 4bit data interface shown in Fig. 11.Although the LCD supports an 8-bit data interface, the Starter Kit board uses a 4-bits data interface to remain compatible with other Xilinx development boards and to minimize total pin count [13].The display on LCD screen needs to make some initialization through the turn on between the FPGA chip and the control unit of LCD screen (LCD controller ST7006U) from Xilinx Company production.The logical circuit of LCD screen is implemented using FPGA.The initialization program of LCD screen is included with VHDL programs using LCD screen as a display unit.Table 1 shows the utilization resources exploited and maximum operating frequency when LCD is implemented on FPGA [7].From Figs. 12, 14, 16 and 18, it can be seen that: 1.One sample is generated at each clock period.

Results and Comparisons
2. The angleselection [3:0] is used as an input from the switches in Spartan-3E board to select the desired angle to generate the digital sine-cosine wave.
3. Ampdigitalsine, Ampdigitalcosine are the amplitudes for digital sine and cosine samples, respectively for the given index time.
4. The vector of bits for Ampdigitalsine, Ampdigitalcosine is [7: -24] for Fig. 12 which means that there are 8 bits for representing the integer part and 24 bits for representing the fractional part in fixed point notation.While in Fig. 14, it can be seen that the vector of bits for Ampdigitalsine, Ampdigitalcosine is [2:-29].This means that there are 3 bits for representing the integer part and 29 bits for representing the fractional part in fixed point notation.And in Figs.
16 and 18, it can be seen that the vector of bits for Ampdigitalsine, Ampdigitalcosine is [1:-30].This means that there are 2 bits for representing the integer part and 30 bits for representing the fractional part in fixed point notation.
The digital sine-cosine generator structures are found through the implementation results to be very appropriate structures from area allocation point of view.The digital sine-cosine generators are implemented using FPGA Spartan-3E device setting the optimization goal of

Resources or Frequency
Total Exploited Allocations for Fig. 2 for Fig. 3 for Fig. 4 for Fig.Time index n Amplitude the synthesizer to be the area, and a comparison is made with other implementations of two recent works given in Refs.[5] and [7].The comparison indicates that smaller area can be achieved when using the designed sine-cosine generator (even with Fig. 5 which has the maximum number of slices among other proposed realizations).In addition, Fig. 5 can operate with an intermediate circuit frequency as compared with the corresponding operating frequencies in the recent works.Table 3 shows the comparison results for the digital sinecosine generator systems.

Conclusions
FPGA implementations of four realizations of single-multiplier digital sine-cosine wave generators have been presented.32-bit word-length for the multiplier coefficient and all outputs of arithmetic operations have been utilized.Such implementations have been compared with other two recent CORDIC-based works.The comparisons have indicated that smaller areas and good operating frequencies can be achieved by the FPGA implementations of the proposed realizations.
The comparison results indicate that smaller FPGA location can be achieved even in the case of one of the worst proposed structures (Fig. 5) of the sine-cosine generator.In addition, such structure can take less FPGA locations and can operate with an intermediate circuit frequency as compared with two of the mentioned recent CORDIC-based implementations.It is believed that the proposed reduced implementation facilitates the use of available technology to generate digital sine-cosine waves.
In the proposed sine-cosine wave generators, it should be noted that due the recursive mode of wave samples generation, the required time for generating a wave sample is proportional to the angle of that sample.Such required time also depends on the initial value of the angle .In spite of such characteristics, the proposed structure can operate in an online application of digital signal modulation systems because the modulation process can be held sequentially with the generation of samples.In addition, the samples of one period of such sine-cosine waves can be transformed from serial to parallel forms for further applications in FFT or DFT structures.Furthermore, the proposed generators have required only one multiplier in their realizations.This means that a sigle quantization process is to be used after multiplication.Also, besides their simple FPGA implementations, it is believed that the proposed generators possess the advantage of uniform frequency spacing.These properties make them suitable for modern communication and electronic applications, such as FFT and IFFT stages in frequency division multiple access (FDMA) systems for small power, small chip resources, and efficient physical implementations of potential multimedia wireless communication systems for fourth generation (4G) technologies.
) requires five multipliers for implementation.The number of multipliers can be reduced to only one by substituting specific values for the constant C. Different single-multiplier realizations are shown in Figs. 2 2, 3, 4 and 5 are shown in the diagrams of Figs. 6, 7, 8 and 9, respectively.

Figures 12 ,
Figures 12, 14, 16 and 18 show the timing diagram of the implementations in Figs. 2, 3, 4 and 5, respectively using ISE9.2isimulator when the input is the (equal to 0.866025404073298) which represents the value of (376CF5D1) in hexadecimal.Two bits are used for integer part and the rest 30 bits are for fractional part.Figs. 13, 15, 17 and 19 show, respectively the output sine and cosine sequences of the structures of Figs. 2, 3, 4 and 5 when the input is .The utilization resources and the maximum frequency used for implementing the structure in Figs. 2, 3, 4, and 5 are shown in Table 2

Fig. 12 Fig. 13
Fig. 12 The timing diagram of the structure in Fig. 2 implementation for  CF D Hex

Fig. 17
Fig. 17 Samples of sine [ ] and cosine [ ]outputs from Fig. 4 for =30° Fig. 16 The timing diagram of the structure in Fig. 4 implementation for  CF D Hex

Table 1
Utilization resources and maximum operating frequency for LCD screen.

Table 2
Utilization resources and maximum frequency of the structure in Figs. 2, 3, 4 and 5.

Table 3
Comparisons with recent implementations of the digital sine-cosine generator systems.