Abstract: frames under C.L
The applications of Discrete Wavelet Transform necessitate fast computation. Full-custom
VLSI devices (ASIC) have been used for fast though expensive implementations of DWT.
Field-Programmable Gate Array (FPGA) architectures offer economical but area-constrained
implementation of DWT. The present paper proposes an important issues on the design and
simulation of ASIC and FPGA architectures for 1-D DWT as well as inverse DWT on a
single chip using VHDL simulation tools. The design of the programmable chip that can be
used as 1-D DWT or IDWT is introduced based on two quadrature mirror filters (QMF), one
used with DWT (decomposition) and other used with IDWT. The design is modular; the chip
can easily be worked as DWT or IDWT with ability of selecting one of the four
corresponding types of QMF wavelet filters (Daubechies 1, 2, 3 and 4).
The first chip is implemented and simulated using FPGA for two word lengths 8-bit and
12-bit respectively. The results show a clock speed of 66.2 MHz for 8-bit, and 55 MHz for
12-bit. While the design of ASIC chip validate a clock speeds 85.5 MHz and 59.2 MHz for
8-bit and 12-bit respectively. Simulation results have established that the higher word length
increase accuracy but at the expense of higher designed size and longest combinational logic
between two storage elements. This means increasing the length of critical path as result of
complexity which decrease the maximum speed clock.
Keywords: VHDL, Wavelet, FPGA, Architecture.