Performance Analysis of Single-Multiplier Digital Sine-Cosine Generators

In this paper, second order structures satisfying single-multiplier digital sine-cosine generators are derived analytically, resulting in four different realizations. Some important characteristics of these generator structures, like total harmonic distortion percentage (THD%), frequency error ( and frequency resolution are defined and examined as performance measures. The four generator realizations are simulated using Matlab7.0 program. The simulation results show that better performance (THD% and are very low or negligible) can be obtained for these realizations by using 32 bits to represent the single-multiplier coefficient and other the outputs of arithmetic operations. The rounding-off method is applied as a quantization process after multiplication process. A comparison is made between one of the best-derived structures and other two recent structures implemented in previous researches. The comparison results indicate that better performance measures can be achieved from the proposed realization for the single-multiplier digital sine-cosine generator.


Introduction
Digital sine-cosine generators are essential elements in many applications.They are used in communications, music synthesis, control, radar, and digital signal processing [1 -7].Stability, flexibility, and low cost are the main advantages of such type of oscillators.Moreover, the parameters of a digitally generated sinusoid are easy to control.A Look-up Table (LUT) is a conventional method for generating desired stable sinusoidal waveforms by storing the amplitude samples in a Read Only Memory (ROM) [.l.], and read them at appropriate time intervals to produce the desired frequency of sinusoidal waves.Other structures for generating digital sinusoidal waveforms are characterized by using a smaller size ROM [2], or by reducing the harmonic distortion of the sine wave by effectively increasing the table length of the direct LUT method to give high resolution [3].A secondorder recursive digital filter can be used for generating digital sinusoidal waves in a critical unstable mode (poles of the digital transfer function lay on the unit circle in the complex zplane).Because of the finite word-length constraints that appear in the practical implementation of all recursive digital oscillators, the multiplier coefficient and the outputs of arithmetic operations must be quantized to fit in the allocated word-length causing amplitude distortion and frequency deviation in the generated sinusoidal waves [4 -5]. A. Abu-El-Haija and M. Al-Ibrahim [6] first reported an improving method for low sensitivity, and low round-off errors performances of digital sinusoidal.A digital sinusoidal oscillator with low and uniform frequency spacing was presented by M. AI-Ibrahim and A. Al-Khateeb [7], but it requires three 14-bit multipliers for its hardware implementation.M. Al-Ibrahim presented then a simple recursive digital sinusoidal oscillator with uniform frequency spacing [8].Nevertheless, such oscillator structure also required a single 14-bit multiplier for its hardware implementation.Again in 2001, M. Al-Ibrahim [9] introduced a multi-frequency range digital sinusoidal oscillator with high resolution and uniform frequency spacing.He modified this work in 2003 for efficient digital oscillator with continuous phase [10].Generators based on parallel and pip line CORDICs were also reported [11 -13].Recently, a vector rotation approach with recording for the design of sinecosine synthesizers was accomplished in 2008 by V. Rankovska [14].In this paper,four different realizations of digital sine-cosine oscillators are derived, and evaluated.32 bits to represent the single-multiplier coefficient and the outputs of arithmetic operations are used.The evaluation results are compared among different derived realizations and between one of the best derived structures and other two recent structures.Such results indicate that better performance measures can be achieved from the proposed realizations.This paper is organized as follows: Besides this introductory section, Section 2 contains the derivation of different realizations of single-multiplier digital sine-cosine generator.Section 3 describes the simulation results for best realization selection depending on different performance measures.A comparative study is given in Section 4 to show the superiority of such realizations with the use of 32 bits word-length over two recent works.Finally, Section 5concludes this paper.

Realizations of Single-Multiplier Digital Sine-Cosine Generator
Different realizations of digital sine-cosine oscillators are considered here.In particular, the derivations of some reduced structures for digital sine-cosine generators that produce the two sinusoidal sequences that are exactly 90 degrees out of phase with each other is first discussed.These circuits have many applications in many signal processing systems such as the computation of the Discrete Fourier Transform (DFT) [8,9].They can also form the backbone of certain orthogonal modulation systems utilized in recent optical and mobile communications.

Let
and denote the two orthogonal outputs of a digital sine-cosine generator, given by [15] and From(1) and ( 2), it can be written that ---(3) And ---(4) Making use of ( 1) and ( 2), ( 3) and ( 4) can be rewritten in matrix form as = So, to obtain and from and , respectively, two delay units are used in the corresponding structure.That is why digital sine-cosine signals can be generated using a second-order recursive digital filter with poles on the unit circle in the complex zplane [9].Thus, it is required to compare (5) with the equivalent expression of a general second-order structure with no delay free loops in order to arrive at a realization of the single-multiplier sine-cosine generator.Such second-order structure is characterized by the following equation [15]: = + Expression (6) can be implemented using five multipliers as shown in Fig. 1 and can be rewritten as in the followings to arrive at the time description of the structure in Fig. 1: ---( 7) and ---(8) Fig.
(1) General second-order structure with no delay free loops.
can also be derived using the same derivations.Then, in matrix form, it can be formulated as = Comparing ( 5) and ( 9 It can be seen that, (12) requires five multipliers for implementation.The number of multipliers can be reduced by substituting specific values for the constant C.This will be discussed in the following subsections: The realization of ( 19) is illustrated in Fig. 3 with an alternate single-multiplier structure.--1

A Single-Multiplier Sine-Cosine Generator By Setting C=0
Another realization of the single-multiplier sine-cosine generator can be obtained by setting another specific value for the multiplier constant (C).That is C=0.Therefore, ( 12

General Form for The Second-Order Difference Equation
As mentioned before, digital sinusoidal signals can be generated using a second-order recursive digital filter with poles on the unit circle in the complex z-plane.The difference equation of the critical unstable digital system representing the direct form digital sine wave oscillator contains one multiplication operation and one subtraction and can be derived as follows [6,9]: Let the generator output be .Then ----( 22) From the homogenous equations, the difference equation of second order can be written as follows: ----(24) The corresponding block diagram representation of ( 24) is shown in Fig. 5.To generate the digital sine-cosine wave, initial values of the variable must be chosen so that the first samples take amplitudes of zero and one for sine and cosine waves, respectively.One of these initials should not be a zero.A zero value is chosen as an initial for the output sine wave , since it starts with zero at .While at is chosen as another initial, since it is a cosine wave.Other amplitudes of the rest samples are generated subsequently according to the previous selected values.For example, if the generator input has an angle ( then the initial values of must be equal to and = and the output is a sine wave .On the other hand, to generate a cosine wave , the initial values of must be changed to and = .In all previous structures, it should be noted that to start the generation of the sinusoidal sequences, one of the signal variables should at least be initially set to a nonzero value.Moreover, the actual amplitudes and the relative phases of the sinusoidal and the cosinusoidal sequences generated by the sine-cosine generator depend on the initial values chosen for the signal variables and It should also be noted that the maximum value of the amplitudes of these two sequences can be made equal by amplitude scaling one of the sequences appropriately.
Single-multiplier structures for sine-cosine generators have many advantages over other structures with many multipliers, such as that the single-multiplier structures retain their characteristic roots on the unit circle under finite word-length constraints.On the other hand, in other realizations of the sine-cosine generators, roots may go inside or outside the unit circle due to the quantization of the multiplier coefficients, causing the oscillations to decay or to build up as increase.In addition, due to product round-off errors, the sequences generated by the sine-cosine generator may not retain their sinusoidal behaviors, even in the case of a single-multiplier generator [7 -10].It is therefore advisable to reset the variables and after some iterations at prescribed time instants, so that the accumulated errors do not become unacceptable.The other advantages of such structures are reducing the --1 --1 Q + chip area used when implemented in hardware, while increasing the speed of such implementations.
In all above-mentioned oscillators, it can also be seen that the desired angle represented by the oscillator coefficient ( is related to the oscillator frequency by ----(24) Where is the desired angular frequency of the generated sinusoid in radians per second, is the desired frequency in cycles per second, and T is the time interval between two consecutive samples of the generated sinusoidal waveform (i.e., the sampling interval).It is also convenient to consider the desired number of samples in a complete cycle of the sinusoidal waveform as Therefore, the smallest frequency which the oscillator can generate is or equivalently, the maximum number of samples per cycle is Where is the minimum desired angle.

Simulation Results for Best Realization Selection
Three important characteristics are used to measure the performance of the designed oscillators.The first characteristic is the percentage of the Total Harmonic Distortion (THD%) which is the ratio of energy in the harmonics to the total energy of the signal [1].or signals can be treated as a periodic discrete time sequence , the calculation of THD% takes the form of [8] where and is the number of samples in an integer number of periods, is the total energy of the waveform, is the energy of the fundamental frequency , is the Discrete Fourier Transform (DFT) of and is the DFT index which is related to the fundamental frequency by The second characteristic of a digital oscillator is the frequency error ( given by [8] ----(33) where is the deviation of the generated frequency from the ideal frequency which resulted from nonlinear behavior of the oscillator, is the desired (ideal) frequency of the wave without error and is the frequency generated by an oscillator structure through the multiplication process of the signal with coefficient as in Figs. 2, 3, 5 and 6.
The last characteristic of digital oscillators, to be examined in this paper, is the frequency deviation ( .It is defined as the difference between two consecutive frequencies.The frequency deviation ( is a measure of claimed uniform frequency spacing and is defined by [8] ----(34) Where.M= It should be noted that, a small frequency deviation is required for a practically usable digital oscillator.The performance measures that are mentioned can be used to describe the efficiency of different single-multiplier digital sine-cosine generators in Figs. 2, 3, 5 and 6 for the selected word-length size of 32 bits.The generators are simulated using Matlab7.0 program and the results are presented in Tables 1-8.The simulation results are obtained assuming a total of 32 bits word-length size for both arithmetic sign and magnitude number representation.The rounding-off quantization process is performed on the result of multiplication process and the initial values are chosen such that and .Tables 1-8 give the values of different angles along with the number of samples per cycle of the generated sinusoidal and co-sinusoidal signals .The frequency of the generated sinusoidal and co-sinusoidal signals and the frequency deviations are calculated assuming a clock frequency of = 50MHzand presented in these tables.The frequency deviation is a measure of the claimed uniform frequency spacing and is specified by (45).The total harmonic distortion percentage THD% and frequency error described by ( 40) and (44), respectively are also presented in Tables 1-8.
From such tables, it can be seen that the maximum value of THD% is obtained when the input angle to the generators is 0.0014649536460638 radian.The maximum values of are produced when the input angle is 0.0014649536460638radian for sine waves but are different for different input angle values for cosine waves.The values of for cosine waves are greater than those for sine waves.The values of ∆ are the same for sine and cosine waves for all input angle values.Also, it can be seen that the maximum values of THD%, (sine) and ∆ are of the same order, while the maximum value of (cosine) is 16.5312Hz for the realization of Fig. 5.The minimum value of (sine) is 0Hz for the realization of Fig. 5. Thus, one can conclude that Fig. 5 is the best realization from the point of view of output errors for different angles.

A Comparative Study
It should be noted that the structures in Figs. 2, 3, 4 and 5 are realized using a word-length size of 32 bits.A comparison is made between the structure in Fig. 5 and other structures implemented in previous researches given in Refs.[8] & [9].The comparison indicates that better performance measures can be achieved from Fig. 5 using the word-length size of 32 bits and rounding-off method as a quantization process after multiplication process.Tables 9  and 10 show the comparison results for the structure in Fig. 5 with those of Refs.[8] & [9].The simulation results and performance measures indicate that THD% and are very low or neglected in the case of the proposed structure in Fig. 5.It should also be noted that the structure in Ref. [8] uses one multiplier for realization and number of bits used to represent the coefficients and variables is 11 bits.The quantization method used after the multiplication process is rounding.While, the structure in Ref. [9] uses two multipliers each with 8 bits and two integrators each with 15 bits for realization to give digital sine-cosine wave.To investigate the effect of word-length size variation, the resulting THD% and in the sinusoidal output of the structure of Fig. 5 are shown, respectively in Figs. 6 and 7 for different 's and different bit representations (8,12,16, 24 and 32 bits)with a clock frequency of 50MHz.From Figs. 6 and 7, it can be noticed that the performance superiority of the 32-bit representation is guaranteed.THD p % and THD 8 % are the total harmonic distortion percentage for the proposed and Ref. [8], respectively.p and 8 are the frequency resolution for the proposed structure in Fig. 5 and that inRef.[8], respectively.Table 10:A comparison with the previous implementation ofRef.[9]for .THD p % and THD 9 % are the total harmonic distortion percentage for the proposed and Ref. [9], respectively.p and 9 are the frequency resolution for the proposed structure in Fig. 5 and that inRef.[9], respectively.

Conclusions
Four realizations of single-multiplier digital sine-cosine generators have been presented form second order structure.It has been shown that the proposed realizations can generate THD%,f error and much lower than those generated by previous works for a 32-bit wordlength of the multiplier coefficient and all outputs of arithmetic operations.The proposed generators have required only one multiplier for their implementations, means that one quantization process is to be done after multiplication process.Therefore, it can be concluded that the implemented digital oscillators exhibit superior performance compared with the oscillators inRefs.[8] and [9].In addition, the proposed generators have the advantage of uniform frequency spacing which makes it suitable for modern communication applications.
), multiple realizations with single-multiplier can be achieved by choosing appropriate values for the two variables ;such as choosing , then (20) can be written as= +It is worth-mentioning thatthe realization of (21) can be accomplished with two multipliers ( .It can be modified to yield a single-multiplier realization as shown in Fig.4.Equivalent structures to that shown in Fig.4can also be derived by setting or by setting .

Table 1 :
Parameters of the structure in Fig.2and the generated sine signal for.

Table 2 :
Parameters of the structure in Fig.2and the generated cosine signal for f clk =50MHz.

Table 3 :
Parameters of the structure in Fig.3and the generated sine signal for .f clk =50MHz

Table 4 :
Parameters of the structure in Fig.3and the generated cosine signal for .f clk =50MHz

Table 5 :
Parameters of the structure in Fig.4and the generated sine signal for f clk =50MHz

Table 6 :
Parameters of the structure in Fig.4and the generated cosine signal for f clk =50MHz.

Table 7 :
Parameters of the structure in Fig.5and the generated sine signal for f clk =50MHz

Table 8 :
Parameters of the structure in Fig.5and the generated cosine signal for f clk =50MHz