Architectural Design of Random Number Generators and Their Hardware Implementations

The architectural design of the random number generators for uniform distribution, normal distribution, exponential distribution and Rayleigh distribution using Box-Muller and inverse transformation method has been hardware implemented on FPGA. Any of the random number generators can generate one sample every clock cycle. The generators have been implemented on Xilinx Spartan 3E XC3S500E FPGA. The designed generators work properly up to maximum frequency of 418.41MHz .The outcome results of the generators have been tested by the chi-square test at a 5% level of significance which provided the correct required distributions. Keyword: Box-mulle, Chi-square, Inverse transformation, FPGA. ةيئاوشعلا ماقرلاا ديلوتل ةيرامعم ميمصت ايدام اهذيفنتو ليعامسإ نيدلا رخف دمرس .د دومحم ركش لساب بوساحلا ةسدنه مسق / لصوملا ةعماج تاينورتكللأأ ةسدنه ةيلك صخلملا ا ديلوتل ةممصملا ةيرامعملا و يعيبط عيزوتو مظتنم عيزوتب ةيئاوشعلا ماقرلا عيزوتو يسا عيزوت لا ةقيرط مادختساب ) يليار( ـ ( Box-muller لا مادختساب ايدام اهءانب مت يسكعلا ليوحتلا ةقيرطو ) FPGA . ىلع اهءانب مت تادلوملا .ةرود لك يف دحاو مقر دلوت نا نكمم ةيئاوشعلا ماقرلاا تادلوم نم دحاو يا Xilinx Spartan 3E XC3S500E FPGA . هرادقم ددرتب لمعلل ةبسانم ةممصملا تادلوملا 418.41MHz ىوتسمب ياك عبرم صحف ةطساوب اهرابتخا مت تادلوملا نم اهيلع لوصحلا مت يتلا جئاتنلا ةيمها اهرادقم 5 .بولطملا عيزوتلا تققح يتلاو % Received: 9 – 5 2013 Accepted: 10 – 10 2013 Al-Rafidain Engineering Vol.22 No. 2 March 2014 51


Introduction
Random number generators are used in a large number of computationally intensive modeling and simulation applications such as traffic light simulation [1],communication system [2],cryptography system [3] ,the most commonly random generators used are uniform distribution, normal distribution ,exponential distribution and Rayleigh distribution.All types of random number generators can be derived from the uniform random generators.The most famous methods for mapping between the generators are Box-muller method and inverse transformation method.
There have been many researches on their hardware implementation to generate random number, A VLSI implementation of universal random number generation with uniform distribution, exponential distribution, Rayleigh distribution and Rayleigh distribution is proposed by CUI, LI and et.al.[4].A hardware Gaussian noise generator using the boxmuller method and the error analysis of its elementary function is proposed by Dong-U, John and et.al.[5], A hardware designs for generating random numbers from arbitrary distributions using the inversion method are proposed by Ray, Dong-U and et.al.[6].A ZIGGURAT based method to generate random number with Gaussian distribution is proposed by Guanglie, Philip and et.al.[7], FPGA implementation and performance analysis of 8, 16, and 32 bit LFSR pseudo random number generator system to generate a uniform distribution is proposed by Amit , Praveena and et.al.[8].A random number is generated by various methods such as LFSR and linear congruental generator and blum blum shub to generate random number with uniform distribution is proposed by Jay, Sudhanshu and et.al.[9].
The paper is organized as follows.In section 2 the background and theory of the architectural design is presented.Section 3 shows the hardware Implementation details.The Experimental results are given in section 4. Section 5 concludes this paper.

Background and Theory
There are many methods to generate random number with arbitrary distribution, most of these method based on converting the random number with uniform distribution to another type of distribution.Review of the methods used in this research is shown below:

Box-muller method:
This method generates a pair of random variables with normal distribution from two uniformly distributions over (0,1) with zero mean and standard deviation =1 (N(0,1)) [10] √ √ U1and U2 are random variables with uniform distributions.X1 and X2 are random variables with a normal distributions.Thus the proposed architecture is based on this method to generate normal distribution.

The inverse transformation method (ITM):
The inversion method for generating non-uniform random variables is based on the simple observation that a random variable X with F as cumulative distribution function (CDF) can be generated by: Where U denotes a uniform U (0, 1) random variable and the X is a random variable with desired distribution [11].
The proposed architectures for exponential distribution and Rayleigh distribution are based on this method.
The required steps to compute the desired random variable using inverse transformation method are: 1-Compute the CDF of the desired random variable X.

and compute
The desired random variable by By applying the above steps for exponential distribution: -Since the PDF (probability density function) for exponential distribution: Then the CDF will be: For more simplicity, because the U is an interval between (0,1) then (1-U) is also an interval between (0,1) and eq.( 7) can be approximated as follows: Repeating the above steps for Rayleigh distribution results: The PDF for Rayleigh distribution: Then its CDF will be: √

Hardware Implementation Details 3.1 Linear Feedback Shift Register (LFSR):
It is a shift register whose input bit is a linear function of its previous state.The most commonly used linear function is XOR.Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value deterministic.The initial value of the LFSR is called the seed.The stream of the values produced by the register is completely determined by its current (or previous) state.Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle.However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.[8][9] [12].
The maximum cycle length of the uniform random variable generated from LFSR is equal -1 where n: is the length of shift register in LFSR.In this paper we use (n=12bit) then the number of random variable = 4k =4096 numbers.
To choose feedback polynomials that generate maximum period we use a table that is presented by Xilinx in [13].The feedback polynomial for 12-bit is Figure 1 shows the architecture design for 12-bit LFSR

The proposed architecture:
Figure 2 shows the design of the proposed architecture.Since it has been used the two 12-bit LFSR to generate two uniform random variables, then look-up table method (LUT) is used to evaluate the two terms in eq. ( 2) for Box-muller method √ and ,since the number of states in LFSR is 4096 state ,then the number of y1 and y2 is also 4096 states and the architecture uses 4 block RAMs in Spartan3E (each block ram is 1k*16bit ) for each term (y1 and y2) then y1 and y2 have use to generate many distribution as shown in figure 2: The LUT circuit is shown in figure 3, the circuit uses 8 block RAMs (4 block RAMs for each term y1 and y2) each block RAM is 1kx16bit .The 30-bit non restoring divider [14] shown in figure( 2) is used to divide the value -lnU1 by lamda ( ) as input in order to generate the exponential distribution.The non-restoring divider technique is used to increase the throughput [14].The Fixed point package [15] is used for representing variables in the VHDL code.Table (1) shows the length and the format of each variable used in the design.The complete architecture design was implemented on Xilinx Spartan 3E XC3S500E FPGA using ISE14.1 and the results of simulation for lamda=2 and sigma=2 are shown in figure 4. It is clear from the simulation results that all the numbers for all distributions are generated in every clock cycle.
The distributions for the generated numbers of the four distributions were plotted as shown in figure 5 using Matlab program.
The distributions for the generated numbers of the four distributions were plotted as shown in figure 5

Speed and resources utilization:
After synthesizing the design by ISE14.1, it is found that the maximum operating frequency becomes 418.41MHz.The resources utilization summary from the FPGA chip is shown in table 2.
To make a fair comparison, Table 3 shows a comparison between our design and three previous related works .These works were implemented on other FPGA target kit so we resynthesized our design on another FPGA target kit as shown in Table 3.

Table (2):
The utilization summary for the proposed design

Figure ( 2 )
Figure (2): The proposed architecture of the random number generators

Table ( 1): Number of Bits Representation for each Element Vol.22 No. 2 March 2014 57
using Matlab program.