Abstract
Abstract
This paper describes a new proposed architecture for tolerating faults in hypercube multiprocessor DSP system. The architecture considered employs the TMS320C40 DSP processors as processing node. The system has a single spare DSP processor assigned to each cluster ( a group of four nodes ). Each pair of clusters share one FPGA unit connected to every node in the two clusters plus the two spare processors. The FPGA units in the system are devoted for data routing, data distributing (in real time processing), diagnosis, system reconfiguration and expanding. Every 3D hypercube has additional spare processors connected to FPGA device of that cube. The spare nodes are used in two stages to tolerate more than one faulty node in each cluster with a low overhead and minimum performance degradation. The system makes use 50% hardware redundancy in the form of spare nodes to achieve fault tolerance. The effectiveness of interprocessor communications and the mechanism of fault detection( for one and two fault ) has been successively simulated using (Xilinx Foundation F2.1i) simulator.
Keywords: Fault Tolerance, Hypercube multiprocessor, TMS320C40, FPGA, DSP processor
