Abstract
Abstract
This paper presents the design of Delta-Sigma ΣΔ based fractional N PLL frequency synthesizer for GSM mobile systems. The loop filter is one of main element in fractional-N ΣΔ synthesizer because it shapes the noise spectrum of quantization error and reduce the spurious level in the pass band of PLL. The effect of loop filter order is studied and it is shown that by increasing the order of the loop filter, the phase noise performance will be improved, although this requires careful design consideration, as the PLL is prone instability. It's shown that the 3rd order loop filter and 3rd order ΣΔ modulator gives the best performance with reducing phase noise (13dBc/Hz ) and spurious noise (44dBc) of the output signal.
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Keyword: PLL, Frequency Synthesizer, ΣΔ Modulator, Fractional-N, GSM mobile systems.
