Abstract
In this paper, a pipeline math processor is designed using VHDL, where doing simulation for processor by using simulation program ISE10.1. The processor is implemented on the FPGA chip in a panel SPARTAN3E, where it has been downloaded by using USB port. The register and buffer memory of each of the fetch and decoder units are designed such that reading and writing operations for the same location are performed during one clock cycle (each clock pulse edge is used for one operation). JTAG port is used to update the data and instructions stored in the main memory via monitor circuit. The main memory of the processor contains two ports, one of them is used to update the data and instructions and the other is used to read data and instructions. For the purpose of increasing the speed, decode and execute units are built so that all operations can be executed in parallel.
The number of operations that can be executed on the processor are 30 operations including triangular functions, hyperbolic functions, square root, ALU, comparison operations, move operation, and parallel shifting and rotation operations. The number of clocks that is required by the mathematical functions, ranges between 17-23 clocks for the first output and then each clock has it's output when the values of input functions are sequential and continuous. The remaining operations (such as addition, subtraction, multiplication and division) need only one clock for each output. The maximum operating frequency for the design chip was found to be 133.820 MHz, therefore its throughput is 133.820 MFlops. For the purpose of displaying all the processor outputs on a computer screen, the VGA Port is used. The overall design of this processor occupies 98% ( when the processor is connected with VGA port) from the volume of the FPGA chip on board SPARTAN3E.
